CMOS超大规模集成电路设计 英文版PDF|Epub|txt|kindle电子书版本网盘下载

CMOS超大规模集成电路设计 英文版PDF格式电子书版下载

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Chapter 1 Welcome to VLSI1

1.1 A Brief History1

1.2 Preview6

1.3 MOS Transistors6

1.4 CMOS Logic9

1.4.1 The Inverter9

1.4.2 The NAND Gate9

1.4.3 CMOS Logic Gates9

1.4.4 The NOR Gate11

1.4.5 Compound Gates11

1.4.6 Pass Transistors and Transmission Gates12

1.4.7 Tristates14

1.4.8 Multiplexers15

1.4.9 Sequential Circuits16

1.5 CMOS Fabrication and Layout19

1.5.1 Inverter Cross-Section19

1.5.2 Fabrication Process20

1.5.3 Layout Design Rules24

1.5.4 Gate Layouts27

1.5.5 Stick Diagrams28

1.6 Design Partitioning29

1.6.1 Design Abstractions30

1.6.2 Structured Design31

1.6.3 Behavioral,Structural,and Physical Domains31

1.7 Example:A Sinple MIPS Microprocessor33

1.7.1 MIPS Architecture33

1.7.2 Multicycle MIPS Microarchitecture34

1.8 Logic Design38

1.8.1 Top-Level Interfaces38

1.8.2 Block Diagrams38

1.8.3 Hierarchy40

1.8.4 Hardware Description Languages40

1.9 Circuit Design42

1.10 Physical Design45

1.10.1 Floorplanning45

1.10.2 Standard Cells48

1.10.3 Pitch Matching50

1.10.4 Slice Plans50

1.10.5 Arrays51

1.10.6 Area Estimation51

1.11 Design Veri.cation53

1.12 Fabrication,Packaging,and Testing54

Summary and a Look Ahead55

Exercises57

Chapter 2 Devices61

2.1 Introduction61

2.2 Long-Channel I-V Characteristics64

2.3 C-V Characteristics68

2.3.1 Simple MOS Capacitance Models68

2.3.2 Detailed MOS Gate Capacitance Model70

2.3.3 Detailed MOS Diffusion Capacitance Model72

2.4 Nonideal I-V Effects74

2.4.1 Mobility Degradation and Velocity Saturation75

2.4.2 Channel Length Modulation78

2.4.3 Threshold Voltage Effects79

2.4.4 Leakage80

2.4.5 Temperature Dependence85

2.4.6 Geometry Dependence86

2.4.7 Summary86

2.5 DC Transfer Characteristics87

2.5.1 Static CMOS Inverter DC Characteristics88

2.5.2 Beta Ratio Effects90

2.5.3 Noise Margin91

2.5.4 Pass Transistor DC Characteristics92

2.6 Pitfalls and Fallacies93

Summary94

Exercises95

Chapter 3 Speed99

3.1 Introduction99

3.1.1 De.nitions99

3.1.2 Timing Optimization100

3.2 Transient Response101

3.3 RC Delay Model104

3.3.1 Effective Resistance104

3.3.2 Gate and Diffusion Capacitance105

3.3.3 Equivalent RC Circuits105

3.3.4 Transient Response106

3.3.5 Elmore Delay108

3.3.6 Layout Dependence of Capacitance111

3.3.7 Determining Effective Resistance112

3.4 Linear Delay Model113

3.4.1 Logical Effort114

3.4.2 Parasitic Delay114

3.4.3 Delay in a Logic Gate116

3.4.4 Drive117

3.4.5 Extracting Logical Effort from Datasheets117

3.4.6 Limitations to the Linear Delay Model118

3.5 Logical Effort of Paths121

3.5.1 Delay in Multistage Logic Networks121

3.5.2 Choosing the Best Number of Stages124

3.5.3 Example126

3.5.4 Summary and Observations127

3.5.5 Limitations of Logical Effort129

3.5.6 Iterative Solutions for Sizing129

3.6 Timing Analysis Delay Models131

3.6.1 Slope-Based Linear Model131

3.6.2 Nonlinear Delay Model132

3.6.3 Current Source Model132

3.7 Pitfalls and Fallacies132

3.8 Historical Perspectives133

Summary134

Exercises134

Chapter 4 Power139

4.1 Introduction139

4.1.1 De.nitions140

4.1.2 Examples140

4.1.3 Sources of Power Dissipation142

4.2 Dynamic Power143

4.2.1 Activity Factor144

4.2.2 Capacitance146

4.2.3 Voltage148

4.2.4 Frequency150

4.2.5 Short-Circuit Current151

4.2.6 Resonant Circuits151

4.3 Static Power152

4.3.1 Static Power Sources152

4.3.2 Power Gating155

4.3.3 Multiple Threshold Voltages and Oxide Thicknesses157

4.3.4 Variable Threshold Voltages157

4.3.5 Input Vector Control158

4.4 Energy-Delay Optimization158

4.4.1 Minimum Energy158

4.4.2 Minimum Energy-Delay Product161

4.4.3 Minimum Energy Under a Delay Constraint161

4.5 Low Power Architectures162

4.5.1 Microarchitecture162

4.5.2 Parallelism and Pipelining162

4.5.3 Power Management Modes163

4.6 Pitfalls and Fallacies164

4.7 Historical Perspective165

Summary167

Exercises167

Chapter 5 Wires169

5.1 Introduction169

5.1.1 Wire Geometry169

5.1.2 Example:Intel Metal Stacks170

5.2 Interconnect Modeling171

5.2.1 Resistance172

5.2.2 Capacitance173

5.2.3 Inductance176

5.2.4 Skin Effect177

5.2.5 Temperature Dependence178

5.3 Interconnect Impact178

5.3.1 Delay178

5.3.2 Energy180

5.3.3 Crosstalk180

5.3.4 Inductive Effects182

5.3.5 An Aside on Effective Resistance and Elmore Delay185

5.4 Interconnect Engineering187

5.4.1 Width,Spacing,and Layer187

5.4.2 Repeaters188

5.4.3 Crosstalk Control190

5.4.4 Low-Swing Signaling192

5.4.5 Regenerators194

5.5 Logical Effort with Wires194

5.6 Pitfalls and Fallacies195

Summary196

Exercises196

Chapter 6 Scaling,Reliability,and Variability199

6.1 Introduction199

6.2 Variability199

6.2.1 Supply Voltage200

6.2.2 Temperature200

6.2.3 Process Variation201

6.2.4 Design Corners202

6.3 Reliability204

6.3.1 Reliability Terminology204

6.3.2 Oxide Wearout205

6.3.3 Interconnect Wearout207

6.3.4 Soft Errors209

6.3.5 Overvoltage Failure210

6.3.6 Latchup211

6.4 Scaling212

6.4.1 Transistor Scaling213

6.4.2 Interconnect Scaling215

6.4.3 International Technology Roadmap for Semiconductors216

6.4.4 Impacts on Design217

6.5 Statistical Analysis of Variability221

6.5.1 Properties of Random Variables221

6.5.2 Variation Sources224

6.5.3 Variation Impacts227

6.6 Variation-Tolerant Design232

6.6.1 Adaptive Control233

6.6.2 Fault Tolerance233

6.7 Pitfalls and Fallacies235

6.8 Historical Perspective236

Summary242

Exercises242

Chapter 7 SPICE245

7.1 Introduction245

7.2 A SPICE Tutorial246

7.2.1 Sources and Passive Components246

7.2.2 Transistor DC Analysis250

7.2.3 Inverter Transient Analysis250

7.2.4 Subcircuits and Measurement252

7.2.5 Optimization254

7.2.6 Other HSPICE Commands256

7.3 Device Models256

7.3.1 Level 1 Models257

7.3.2 Level 2 and 3 Models258

7.3.3 BSIM Models258

7.3.4 Diffusion Capacitance Models258

7.3.5 Design Comers260

7.4 Device Characterization261

7.4.1 I-V Characteristics261

7.4.2 Threshold Voltage264

7.4.3 Gate Capacitance266

7.4.4 Parasitic Capacitance266

7.4.5 Effective Resistance268

7.4.6 Comparison of Processes269

7.4.7 Process and Environmental Sensitivity271

7.5 Circuit Characterization271

7.5.1 Path Simulations271

7.5.2 DC Transfer Characteristics273

7.5.3 Logical Effort273

7.5.4 Power and Energy276

7.5.5 Simulating Mismatches277

7.5.6 Monte Carlo Simulation277

7.6 Interconnect Simulation277

7.7 Pitfalls and Fallacies280

Summary282

Exercises282

Chapter 8 Gates285

8.1 Introduction285

8.2 Circuit Families286

8.2.1 Static CMOS287

8.2.2 Ratioed Circuits292

8.2.3 Cascode Voltage Switch Logic297

8.2.4 Dynamic Circuits297

8.2.5 Pass-Transistor Circuits307

8.3 Circuit Pitfalls312

8.3.1 Threshold Drops313

8.3.2 Ratio Failures313

8.3.3 Leak age314

8.3.4 Charge Sharing314

8.3.5 Power Supply Noise314

8.3.6 Hot Spots315

8.3.7 Minority Carrier Injection315

8.3.8 Back-Gate Coupling316

8.3.9 Diffusion Input Noise Sensitivity316

8.3.10 Process Sensitivity316

8.3.11 Example:Domino Noise Budgets317

8.4 Silicon-On-Insulator Circuit Design318

8.4.1 Floating Body Voltage319

8.4.2 SOI Advantages320

8.4.3 SOI Disadvantages320

8.4.4 Implications for Circuit Styles321

8.4.5 Summary322

8.5 Subthreshold Circuit Design322

8.5.1 Sizing323

8.5.2 Gate Selection323

8.6 Pitfalls and Fallacies324

8.7 Historical Perspective325

Summary327

Exercises328

Chapter 9 Sequencing333

9.1 Introduction333

9.2 Sequencing Static Circuits334

9.2.1 Sequencing Methods334

9.2.2 Max-Delay Constraints337

9.2.3 Min-Delay Constraints341

9.2.4 Time Borrowing344

9.2.5 Clock Skew347

9.3 Circuit Design of Latches and Flip-Flops349

9.3.1 Conventional CMOS Latches350

9.3.2 Conventional CMOS Flip-Flops351

9.3.3 Pulsed Latches353

9.3.4 Resettable Latches and Flip-Flops354

9.3.5 Enabled Latches and Flip-Flops355

9.3.6 Incorporating Logic into Latches356

9.3.7 Klass Semidynamic Flip-Flop(SDFF)357

9.3.8 Differential Flip-Flops357

9.3.9 Dual Edge-Triggered Flip-Flops358

9.3.10 Radiation-Hardened Flip-Flops359

9.4 Static Sequencing Element Methodology360

9.4.1 Choice of Elements361

9.4.2 Characterizing Sequencing Element Delays363

9.4.3 State Retention Registers366

9.4.4 Level-Converter Flip-Flops366

9.4.5 Design Margin and Adaptive Sequential Elements367

9.5 Synchronizers369

9.5.1 Metastability370

9.5.2 A Simple Synchronizer373

9.5.3 Communicating Between Asynchronous Clock Domains374

9.5.4 Common Synchronizer Mistakes375

9.5.5 Arbiters377

9.5.6 Degrees of Synchrony377

9.6 Wave Pipelining378

9.7 Pitfalls and Fallacies380

Summary381

Exercises383

Chapter 10 Datapaths387

10.1 Introduction387

10.2 Addition/Subtraction387

10.2.1 Single-Bit Addition388

10.2.2 Carry-Propagate Addition392

10.2.3 Subtraction416

10.2.4 Multiple-Input Addition416

10.2.5 Flagged Prefix Adders417

10.3 One/Zero Detectors419

10.4 Comparators420

10.4.1 Magnitude Comparator420

10.4.2 Equality Comparator420

10.4.3 K＝A+B Comparator421

10.5 Counters421

10.5.1 Binary Counters422

10.5.2 Fast Binary Counters423

10.5.3 Ring and Johnson Counters424

10.5.4 Linear-Feedback Shift Registers424

10.6 Boolean Logical Operations426

10.7 Coding426

10.7.1 Parity426

10.7.2 Error-Correcting Codes426

10.7.3 Gray Codes428

10.7.4 XOR/XNOR Circuit Forms429

10.8 Shifters430

10.8.1 Funnel S hifter431

10.8.2 Barrel Shifter433

10.8.3 Alternative Shift Functions434

10.9 Multiplication434

10.9.1 Unsigned Array Multiplication436

10.9.2 Two's Complement Array Multiplication437

10.9.3 Booth Encoding438

10.9.4 Column Addition443

10.9.5 Final Addition447

10.9.6 Fused Multiply-Add448

10.9.7 Summary448

10.10 Parallel-Prefix Computations449

10.11 Pitfalls and Fallacies451

Summary452

Exercises452

Chapter 11 Memories455

11.1 Introduction455

11.2 SRAM456

11.2.1 SRAM Cells457

11.2.2 Row Circuitry464

11.2.3 Column Circuitry468

11.2.4 Multi-Ported SRAM and Register Files472

11.2.5 Large SRAMs473

11.2.6 Low-Power SRAMs475

11.2.7 Area,Delay,and Power of RAMs and Register Files478

11.3 DRAM480

11.3.1 Subarray Architectures481

11.3.2 Column Circuitry483

11.3.3 Embedded DRAM484

11.4 Read-Only Memory485

11.4.1 Programmable ROMs487

11.4.2 NAND ROMs488

11.4.3 Flash489

11.5 Serial Access Memories491

11.5.1 Shift Registers491

11.5.2 Queues(FIFO,LIFO)491

11.6 Content-Addressable Memory493

11.7 Programmable Logic Arrays495

11.8 Robust Memory Design499

11.8.1 Redundancy499

11.8.2 Error Correcting Codes(ECC)501

11.8.3 Radiation Hardening501

11.9 Historical Perspective501

Summary503

Exercises504

Chapter 12 Packaging,Power,Clock,I/O507

12.1 Introduction507

12.2 Packaging and Cooling507

12.2.1 Package Options507

12.2.2 Chip-to-Package Connections509

12.2.3 Package Parasitics510

12.2.4 Heat Dissipation510

12.2.5 Temperature Sensors511

12.3 Power Distribution513

12.3.1 On-Chip Power Distribution Network514

12.3.2 IR Drops515

12.3.3 L di/dt Noise516

12.3.4 On-Chip Bypass Capacitance517

12.3.5 Power Network Modeling518

12.3.6 Power Supply Filtering522

12.3.7 Charge Pumps522

12.3.8 Substrate Noise523

12.3.9 Energy Scavenging523

12.4 Clocks524

12.4.1 De.nitions524

12.4.2 Clock System Architecture526

12.4.3 Global Clock Generation527

12.4.4 Global Clock Distribution529

12.4.5 Local Clock Gaters533

12.4.6 Clock Skew Budgets535

12.4.7 Adaptive Deskewing537

12.5 PLLs and DLLs538

12.5.1 PLLs538

12.5.2 DLLs545

12.5.3 Pitfalls547

12.6 I/O548

12.6.1 Basic I/O Pad Circuits549

12.6.2 Electrostatic Discharge Protection551

12.6.3 Example:MOSIS I/O Pads552

12.6.4 Mixed-Voltage I/O554

12.7 High-Speed Links555

12.7.1 High-Speed I/O Channels555

12.7.2 Channel Noise and Interference558

12.7.3 High-Speed Transmitters and Receivers559

12.7.4 Synchronous Data Transmission564

12.7.5 Clock Recovery in Source-Synchronous Systems564

12.7.6 Clock Recovery in Mesochronous Systems566

12.7.7 Clock Recovery in Pleisochronous Systems568

12.8 Random Circuits568

12.8.1 True Random Number Generators568

12.8.2 Chip Identification569

12.9 Pitfalls and Fallacies570

Summary571

Exercises572

Chapter 13 Methodology573

13.1 Introduction573

13.2 Structured Design Strategies575

13.2.1 A Software Radio—A System Example576

13.2.2 Hierarchy578

13.2.3 Regularity581

13.2.4 Modularity583

13.2.5 Locality584

13.2.6 Summary585

13.3 Design Methods585

13.3.1 Microprocessor/DSP585

13.3.2 Programmable Logic586

13.3.3 Gate Arrayand Sea of Gates Design589

13.3.4 Cell-Based Design590

13.3.5 Full Custom Design592

13.3.6 Platform-Based Design—System on a ChiP593

13.3.7 Summary594

13.4 Design Flows594

13.4.1 Behavioral Synthesis Design Flow(ASIC Design Flow)595

13.4.2 Automated Layout Generation599

13.4.3 Mixed-Signal or Custom-Design Flow603

13.5 Design Economics604

13.5.1 Non-Recurring Engineering Costs(NREs)605

13.5.2 Recurring Costs607

13.5.3 Fixed Costs608

13.5.4 Schedule609

13.5.5 Personpower611

13.5.6 Project Management611

13.5.7 Design Reuse612

13.6 Data Sheets and Documentation613

13.6.1 The Summary613

13.6.2 Pinout613

13.6.3 Description of Operation613

13.6.4 DC Specifications613

13.6.5 AC Specifications614

13.6.6 Package Diagram614

13.6.7 Principles of Operation Manual614

13.6.8 User Manual614

13.7 Pitfalls and Fallacies615

Exercises615

Chapter 14 Test617

14.1 Introduction617

14.1.1 Logic Veri.cation618

14.1.2 Debugging620

14.1.3 Manufacturing Tests622

14.2 Testers,Test Fixtures,and Test Programs624

14.2.1 Testers and Test Fixtures624

14.2.2 Test Programs626

14.2.3 Handlers627

14.3 Logic Verification Principles628

14.3.1 Test Vectors628

14.3.2 Testbenches and Harnesses629

14.3.3 Regression Testing629

14.3.4 Version Control630

14.3.5 Bug Tracking631

14.4 Silicon Debug Principles631

14.5 Manufacturing Test Principles634

14.5.1 Fault Models635

14.5.2 Observability637

14.5.3 Controllability637

14.5.4 Repeatability637

14.5.5 Survivability637

14.5.6 Fault Coverage638

14.5.7 Automatic Test Pattern Generation(ATPG)638

14.5.8 Delay Fault Testing638

14.6 Design for Testability639

14.6.1 Ad Hoc Testing639

14.6.2 Scan Design640

14.6.3 Built-In Self-Test(BIST)642

14.6.4 IDDQ Testing645

14.6.5 Design for Manufacturability645

14.7 Boundary Scan646

14.8 Testing in a University Environment647

14.9 Pitfalls and Fallacies648

Summary655

Exercises655

Chapter 15 Fabrication657

15.1 Introduction657

15.2 CMOS Technologies658

15.2.1 Wafer Formation658

15.2.2 Photolimography659

15.2.3 Well and Channel Formation661

15.2.4 Silicon Dioxide(SiO2)663

15.2.5 Isolation664

15.2.6 Gate Oxide665

15.2.7 Gate and Source/Drain Formations666

15.2.8 Contacts and Metallization668

15.2.9 Passivation670

15.2.10 Metrology670

15.3 Layout Design Rules671

15.3.1 Design Rule Background671

15.3.2 Scribe Line and Other Stnctures674

15.3.3 MOSIS Scalable CMOS Design Rules675

15.3.4 Micron Design Rules676

15.4 CMOS Process Enhancements677

15.4.1 Transistors677

15.4.2 Interconnect680

15.4.3 Circuit Elements682

15.4.4 Beyond Conventional CMOS687

15.5 Technology-Related CAD Issues688

15.5.1 Design Rule Checking(DRC)689

15.5.2 Circuit Extraction690

15.6 Manufacturing Issues691

15.6.1 Antenna Rules691

15.6.2 LayerDensitv Rules692

15.6.3 Resolution Enhancement Rules692

15.6.4 Metal Slotting Rules693

15.6.5 Yield Enhancement Guidelines693

15.7 Pitfalls and Fallacies694

15.8 Historical Perspective695

Summary697

Exercises697

References699

Index731

Credits751