图书介绍
CMOS Digital Integrated Circuits：Analysis and Design （Third Edition）PDF|Epub|txt|kindle电子书版本网盘下载
- Sung-Mo Kang Yusuf Leblebici著 著
- 出版社： 清华大学出版社
- ISBN：7302090602
- 出版时间：2004
- 标注页数：626页
- 文件大小：34MB
- 文件页数：643页
- 主题词：数字集成电路－电路分析－高等学校－教材－英文；数字集成电路－电路设计－高等学校－教材－英文
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图书目录
Chapter1 Introduction1
1.1 Historical Perspective1
1.2 Objective and Organization of the Book5
1.3 A Circuit Design Example8
1.4 Overview of VLSI Design Methodologies18
1.5 VLSI Design Flow21
1.6 Design Hierarchy23
1.7 Concepts of Regularity,Modularity,and Locality25
1.8 VLSI Design Styles28
1.9 Design Quality38
1.10 Packaging Technology41
1.11 Computer-Aided Design Technology43
Exercise Problems45
Chapter2 Fabrication of MOSFETs48
2.1 Introduction48
2.2 Fabrication Process Flow:Basic Steps49
2.3 The CMOS n-Well Process59
2.4 Layout Design Rules66
2.5 Full-Custom Mask Layout Design66
Exercise Problems73
Chapter3 MOS Transistor83
3.1 The Metal Oxide Semiconductor(MOS)Structure83
3.2 The MOS System under Extemal Bias87
3.3 Structure and Operation of MOS Transistor(MOSFET)90
3.4 MOSFET Current-Voltage Characteristics100
3.5 MOSFET Scaling and Small-Geometry Effects112
3.6 MOSFET Capacitances126
Exercise Problems138
Chapter4 Modeling of MOS Transistors Using SPICE143
4.1 Introduction143
4.2 Basic Concepts144
4.3 The LEVEL 1 Model Equations146
4.4 The LEVEL 2 Model Equations150
4.5 The LEVEL 3 Model Equations154
4.6 State-of-the-Art MOSFET Models155
4.7 Capacitance Models156
4.8 Comparison of the SPICE MOSFET Models160
Appendix:Typical SPICE Model Parameters162
Exercise Problems165
Chapter5 MOS Inverters:Static166
Characteristics166
5.1 Introduction166
5.2 Resistive-Load Inverter174
5.3 Inverters with n-Type MOSFET Load183
5.4 CMOS Inverter194
Exercise Problems211
Chapter6 MOS Inverters:Switching Characteristics and Interconnect Effects215
6.1 Introduction215
6.2 Delay-Time Definitions217
6.3 Calculation of Delay Times219
6.4 Inverter Design with Delay Constraints227
6.5 Estimation of Interconnect Parasitics238
6.6 Calculation of Interconnect Delay249
6.7 Switching Power Dissipation of CMOS Inverters257
Appendix:Super Buffer Design264
Exercise Problems267
Chapter7 Combinational MOS Logic Circuits271
7.1 Introduction271
7.2 MOS Logic Circuits with Depletion nMOS Loads272
7.3 CMOS Logic Circuits284
7.4 Complex Logic Circuits291
7.5 CMOS Transmission Gates(Pass Gates)304
Exercise Problems314
Chapter8 Sequential MOS Logic Circuits320
8.1 Introduction320
8.2 Behavior of Bistable Elements321
8.3 SR Latch Circuit327
8.4 Clocked Latch and Flip-Flop Circuits333
8.5 CMOS D-Latch and Edge-Triggered Flip-Flop340
Appendix:Schmitt Trigger Circuit347
Exercise Problems350
Chapter9 Dynamic Logic Circuits354
9.1 Introduction354
9.2 Basic Principles of Pass Transistor Circuits356
9.4 Synchronous Dynamic Circuit Techniques368
9.5 Dynamic CMOS Circuit Techniques373
9.6 High-Performance Dynamic CMOS Circuits377
Exercise Problems394
Chapter10 Semiconductor Memories399
10.1 Introduction399
10.2 Dynamic Random Access Memory(DRAM)404
10.3 Static Random Access Memory(SRAM)432
10.4 Nonvolatile Memory445
10.5 Flash Memory458
10.6 Ferroelectric Random Access Memory(FRAM)466
Exercise Problems469
Chapter11 Low-Power CMOS Logic Circuits475
11.1 Introduction475
11.2 Overview of Power Consumption476
11.3 Low-Power Design Through Voltage Scaling487
11.4 Estimation and Optimization of Switching Activity498
11.5 Reduction of Switched Capacitance504
Exercise Problems506
Chapter12 BiCMOS Logic Circuits507
12.1 Introduction507
12.2 Bipolar Junction Transistor(BJT):Structure and Operation510
12.3 Dynamic Behavior of BJTs522
12.4 Basic BiCMOS Circuits:Static Behavior529
12.5 Switching Delay in BiCMOS Logic Circuits531
12.6 BiCMOS Applications537
Exercise Problems540
Chapter13 Chip Input and Output(I/O)544
Circuits544
13.1 Introduction544
13.2 ESD Protection545
13.3 Input Circuits548
13.4 Output Circuits and L(di/dt)Noise553
13.5 On-Chip Clock Generation and Distribution557
13.6 Latch-Up and Its Prevention562
Exercise Problems569
Chapter14 Design for Manufacturability571
14.1 Introduction571
14.2 Process Variations572
14.3 Basic Concepts and Definitions574
14.4 Design of Experiments and Performance Modeling580
14.5 Parametric Yield Estimation588
14.6 Parametric Yield Maximization593
14.7 Worst-Case Analysis595
14.8 Performance Variability Minimization601
Exercise Problems604
Chapter15 Design for Testability608
15.1 Introduction608
15.2 Fault Types and Models608
15.3 Controllability and Observability612
15.4 Ad Hoc Testable Design Techniques613
15.5 Scan-Based Techniques616
15.6 Built-In Self Test(BIST)Techniques618
Exercise Problems622
References623