计算机组织与结构 性能设计 英文版PDF|Epub|txt|kindle电子书版本网盘下载

计算机组织与结构 性能设计 英文版PDF格式电子书版下载

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Chapter 0 Reader’s Guide1

0.1 Outline of the Book2

0.2 A Roadmap for Readers and Instructors2

0.3 Why Study Computer Organization and Architecture3

0.4 Internet and Web Resources4

PART ONE OVERVIEW7

Chapter 1 Introduction8

1.1 Organization and Architecture9

1.2 Structure and Function10

1.3 Key Terms and Review Questions15

Chapter 2 Computer Evolution and Performance16

2.1 A Brief History of Computers17

2.2 Designing for Performance38

2.3 The Evolution of the Intel x86 Architecture44

2.4 Embedded Systems and the ARM46

2.5 Performance Assessment50

2.6 Recormnended Reading and Web Sites57

2.7 Key Terms，Review Questions，and Problems59

PART TWO THE COMPUTER SYSTEM63

Chapter 3 A Top-LevelView of Computer Function and Interconnection65

3.1 Computer Components66

3.2 Computer Function68

3.3 Interconnection Structures83

3.4 Bus Interconnection85

3.5 PCI95

3.6 Recommended Reading and Web Sites104

3.7 Key Terms，Review Questions，and Problems104

Appendix 3A Timing Diagrams108

Chapter 4 Cache Memory110

4.1 Computer Memory System Overview111

4.2 Cache Memory Principles118

4.3 Elements of Cache Design121

4.4 Pentium 4 Cache Organization140

4.5 ARM Cache Organization143

4.6 Recommended Reading145

4.7 Key Terms，Review Questions，and Problems146

Appendix 4A Performance Characteristics of Two-Level Memories151

Chapter 5 Internal Memory Technology158

5.1 Semiconductor Main Memory159

5.2 Error Correction169

5.3 Advanced DRAM Organization173

5.4 Recommended Reading and Web Sites179

5.5 Key Terms，Review Questions，and Problems180

Chapter 6 External Memory184

6.1 Magnetic Disk185

6.2 RAID194

6.3 Optical Memory203

6.4 Magnetic Tape210

6.5 Recommended Reading and Web Sites212

6.6 Key Terms，Review Questions，and Problems214

Chapter 7 Input/Output217

7.1 External Devices219

7.2 I/O Modules222

7.3 Programmed I/O224

7.4 Interrupt-Driven I/O228

7.5 Direct Memory Access236

7.6 I/O Channels and Processors242

7.7 The External Interface：Fire Wire and Infiniband244

7.8 Recommended Reading and Web Sites253

7.9 Key Terms，Review Questions，and Problems254

Chapter 8 Operating System Support259

8.1 Operating System Overview260

8.2 Scheduling271

8.3 Memory Management277

8.4 Pentium Memory Management288

8.5 ARM Memory Management293

8.6 Recommended Reading and Web Sites298

8.7 Key Terms，Review Questions，and Problems299

PART THREE THE CENTRAL PROCESSING UNIT303

Chapter 9 Computer Arithmetic305

9.1 The Arithmetic and Logic Unit （ALU）306

9.2 Integer Representation307

9.3 Integer Arithmetic312

9.4 Floating-Point Representation327

9.5 Floating-Point Arithmetic334

9.6 Recommended Reading and Web Sites342

9.7 Key Terms，Review Questions，and Problems344

Chapter 10 Instruction Sets：Characteristics and Functions348

10.1 Machine Instruction Characteristics349

10.2 Types of Operands356

10.3 Intel x86 and ARM Data Types358

10.4 Types of Operations362

10.5 Intel x86 and ARM Operation Types374

10.6 Recommended Reading384

10.7 Key Terms，Review Questions，and Problems385

Appendix 10A Stacks390

Appendix 10B Little，Big，and Bi-Endian396

Chapter 11 Instruction Sets：Addressing Modes and Formats400

11.1 Addressing401

11.2 x86 and ARM Addressing Modes408

11.3 Instruction Formats413

11.4 x86 and ARM Instruction Formats421

11.5 Assembly Language426

11.6 Recommended Reading428

11.7 Key Terms，Review Questions，and Problems428

Chapter 12 Processor Structure and Function432

12.1 Processor Organization433

12.2 Register Organization435

12.3 The Instruction Cycle440

12.4 Instruction Pipelining444

12.5 The x86 Processor Family461

12.6 The ARM Processor469

12.7 Recommended Reading475

12.8 Key Terms，Review Questions，and Problems476

Chapter 13 Reduced Instruction Set Computers （RISCs）480

13.1 Instruction Execution Characteristics482

13.2 The Use of a Large Register File487

13.3 Compiler-Based Register Optimization492

13.4 Reduced Instruction Set Architecture494

13.5 RISC Pipelining500

13.6 MIPS R4000504

13.7 SPARC511

13.8 The RISC versus CISC Controversy517

13.9 Recommended Reading518

13.10 Key Terms，Review Questions，and Problems518

Chapter 14 Instruction-Level Parallelism and Superscalar Processors522

14.1 Overview524

14.2 Design Issues528

14.3 Pentium 4538

14.4 ARM Cortex-A8544

14.5 Recommended Reading552

14.6 Key Terms，Review Questions，and Problems554

PART FOUR THE CONTROL UNIT559

Chapter 15 Control Unit Operation561

15.1 Micro-operations563

15.2 Control of the Processor569

15.3 Hardwired Implementation581

15.4 Recommended Reading584

15.5 Key Terms，Review Questions，and Problems584

Chapter 16 Microprogrammed Control586

16.1 Basic Concepts587

16.2 Microinstruction Sequencing596

16.3 Microinstruction Execution602

16.4 TI 8800614

16.5 Recommended Reading624

16.6 Key Terms，Review Questions，and Problems625

PART FIVE PARALLEL ORGANIZATION627

Chapter 17 Parallel Processing628

17.1 The Use of Multiple Processors630

17.2 Symmetric Multiprocessors632

17.3 Cache Coherence and the MESI Protocol640

17.4 Multithreading and Chip Multiprocessors646

17.5 Clusters653

17.6 Nonuniform Memory Access Computers660

17.7 Vector Computation664

17.8 Recommended Reading and Web Sites676

17.9 Key Terms，Review Questions，and Problems677

Chapter 18 Multicore Computers684

18.1 HardwarePerformance Issues685

18.2 Software Performance Issues690

18.3 Multicore Organization694

18.4 Intel x86 Multicore Organization696

18.5 ARM11 MPCore699

18.6 Recommended Reading and Web Sites704

18.7 Key Terms，Review Questions，and Problems705

Appendix A Projects for Teaching Computer Organization and Architecture707

A.1 Interactive Sinmlations708

A.2 Research Projects708

A.3 Simulation Projects710

A.4 Assembly Language Projects711

A.5 Reading/Report Assigmnents711

A.6 Writing Assigmnents712

A.7 Test Bank712

Appendix B Assembly Language and Related Topics713

B.1 Assembly Language714

B.2 Assemblers723

B.3 Loading and Linking728

B.4 Recommended Reading and Web Sites735

B.5 Key Terms，Review Questions，and Problems736

Appendix C Hash Tables740

Appendix D Victim Cache Strategies740

Appendix E Interleaved Memory740

Appendix F International Reference Alphabet740

Appendix G Virtual Memory Page Replacement Algorithms740

Appendix H Recursive Procedures740

Appendix I Additional Instruction Pipeline Topics740

Appendix J Linear Tape Open Technology740

AppendiX K DDR SDRAM740

Glossary740

References750

Index763